Blue Flower

While I was backuping data, I found documents that I written between after my college graduation and before I continued study abroad. So I might as well post them and write an article about them. Basically, I was stressed because I was pushed without rest to find a job, then I had no choice but to take a stressing job, and finally resigned because I got accepted in studying abroad.

Insanely Applied to Valve

applying valve blizzard

I was a gamer back then especially when my friends were also gamers. The games that we played back then are mostly from Steam. On their website, the job menu was always there and back then was emphasized. Their book about their job was also open electronically. The most interesting thing that I remembered that their company's structure was dynamic. Everyone can come up with a project and the structure will be made after the approval of the project and once the project finishes, the structure changes based on the next project. As I was desperate back then, I did not think twice to apply, and what is the disadvantage of just applying. Here is my cover letter when I was applying:

I would like to apply for the position in network/system engineer. In the past I have dealt with simple local area network until complex network in certain agencies. I started when I was an undergraduate student in a computer lab learning ip address configuration, twisted pair cables and simple switches. Then I got to be part of a project in installing fiber optic cable for whole central government regency of Badung. I was a staff supervisor under CV Bali Info data which my job description was reporting every detail of the project's development to the heads of the project. With three of my friends we witness the whole work from June to August 2012 everyday, starting from planting the cable underground, splicing, to network configuration. My friends wrote an analysis about the cabling, such as the splicing and the OTDR test result, while I took interest and specialize in network configuration. I wrote a report and made a simulation of how the networks were configured. The simulation I made in Cisco Packet Tracer because all the network equipments are Cisco Devices. I didn't take part in the network con guration because I was a staff supervisor, not the engineer. But I examined thouroughly how the network engineer back then configured the network and afterwards I decided to learn networking on my own. A year after the project was finished a new project came up that was to install wireless access point throughout the regency. I was very lucky that they chose me to configure the network which was to synchronize the wireless access point to the current network. I was given full access and ultimately I master all the network configuration back then. Around that year I was constantly called whenever there was trouble in the network. It's thanks to this experience I can start my career as a network engineer.

After that I got interested in Linux and Open Source software. At first I was interested in penetration testing (pentest) using Backtrack and Kali Linux, but since I was quite busy with my final project on my last semester I have to stop in intensive in pentest. Back then most of my time was spent on C programming and Linux Embedded on Imote2 wireless sensor network for my final project. So up till now I'm interested in using Linux as primary operating system, as you now in Indonesia most people rely on cracked softwares. I used to be one them until I learned of open source software, so I tried to removed my reliance to cracked software. In the process I also stumbled on servers using Linux. Right after I finished my final project one of my friends asked for my help in his final project about dynamic adaptive streaming over http (DASH). I was asked to install a web server using Ubuntu, convert mp4 video to mpd file format, and prepare the live dash client on the web server to play the mpd file online. Today I voluntarily help the IT staff at Udayana University to configure a Mikrotik device to function as a bandwidth manager and firewall for the network while waiting to further my career.

I see Valve Corporation as a potential place where I could further my career. To be honest I knew Valve because I was a gamer, I played counter strike in the past and today I enjoyed playing DOTA 2 with my friends. The truth is as a network engineer I could always apply in other IT corporations or providers but since I have a background as a gamer I would like to know and experience working in a game corporation such as Valve, also as a way I would like to support gaming industry. I have a deep interest in the corporation. Here I apply as a network engineer where I could do best in but also I was hoping to get the chance to witness and be involve in making games. I was hoping I could work as a network engineer while learning how games were produced. In conclusion other than I think I'm suited for this position, I have high motivation to be working with Valve Corporation.

Ofcourse I was mad to even apply. Who would want a fresh graduate residing in another country who does not have any special talent? The expenses would far outnumbered the benefit of them hiring me. Yes, without any details, they just rejected me. At the same time I applied to Blizzard as well and the same result. In this period, I also applied to Smartfren Telecommunication Service Provider because there were news about its open recruitment in the newspaper but also does not sit well for me since they were looking for experts in telecommunication network while I only have experience in computer networks.

Well Known Scholarships Back Then

scholarships

I enjoyed my college studies and felt more fun doing learning and researching and therefore even before I graduate, I already planned to continue to graduate school and get the highest degree while enjoying studying. My other agenda is to travel abroad and be in an international environment. If you read my post about deals going to school, you have probably read of how much I despise student loans because unless you are able steer the wheels, you will probably end up a slave struggling to repay your debts. On that post I also wrote that the best way to continue studying is to get a scholarship. In this period, I was applying to many scholarships and the globally popular ones back then are:

Yes there are more scholarships but back then they are not generally know, at least in my ears. You can searching for scholarships in each country for example try the search terms "scholarship in China", "scholarship in Russia", "scholarship in Germany", "scholarship in Netherland", etc. Generally, the requirements are:

  1. Identity, degree, transcript, and other essential documents.
  2. English certificates such as TOEFL and IELTS.
  3. Letter of recommendation.
  4. Curiculum Vitae (CV) and other certificates.
  5. Research Proposal.

For graduate school in my experience is that other requirments are enough with just the bare minimum. What is most important is the research proposal because in reflects out plan for the whole study, what will we do there, and what will we contribute for them. Graduate school is different from the spoon feeding of primary and high school, it is different from college where we are to observe and learn where those who did well in exams are prefered as these people can be taught much more easily. In graduate school, they are not interested in teaching us but they look forward to our contribution to their research and if possible for us to lead.

The following cover letter is the one that I submitted to Erasmus Mundus:

I have just graduated from Undergraduate School of Electrical Engineering Udayana University and I plan to continue my study for master dagree overseas. There are few reasons why I would like to study abroad, the main reason is because I wanted to see more parts of the world, another reason is I missed the days when I was in elementary school in Australia where there was a large diversity of people. In other words the school consists of people from different parts of the world. Back then I found it fun and interesting in getting to know different kinds of people. Therefore I decided that I would like to experience the sensation again after I obtain my Bachelor dagree. When I heard of ERASMUS MUNDUS Pervasive Computing and Communications for Sustainable Development (PERCCOM) I didn’t need to think twice to apply for it. Not only it fits my background, the program itself I find it very interersting, especially the part where we get to study in different parts of Europe which are University of Lorraine (France), Lappeenranta University of Technology (Finland), Lulea University of Technology (Sweden), St Petersburg University of Mechanics and Optics (Russia), maybe there are other places as well (from the information I read from PERCCOM website). If I were to join this program I could get to know variety of cultures and people, and most importantly I will have the opportunity to befriend with people from all over the world.

Eventhough my background is in electrical, I concentrated in the field of telecommunication, and also I’m very familiar with networking and programming because they were one of my hobbies. I was taught the basics of electrical and telecommunication but I ran deep into networking and programming, in the end my final project relied heavily on programming with a bit electrical and communication analysis thus it can be catagorized to energy efficiency in ICT. For two and a half year as I spent as a lab assistant in both Computer Lab and Communication System Lab, I was entrusted as the network engineer of those two labs. So I thought I could continue my study from my undergraduate studies in green ICT through this program. I read from many articles and papers that most of the worlds energy resources are being consumed by ICT. By continuing studying in ICT I may be able to take part in solving this problem. In the future not only I want to improve the capabilities of ICT but also I would like to make it cleaner, green, and more efficient.

I was rejected for Erasmus Mundus scholarship. With my experience now, looking back at the cover letter that I wrote it contained my motivation to study and my agenda of being in an international environment. You don't study information communication technology (ICT) in graduate school. You study that in undergraduate school or anyone else can study by themselves. While recruiting students from abroad does fulfill the purpose of making a more international environment but is never the primary purpose. The primary purpose of graduate school is to find students who can contribute where in this case I lack proposal in my cover letter.

The following I submitted to Fullbright and Australian Awards:

I have graduated and received my bachelor in electrical engineering concentrated in telecommunication just a few months ago. I'm interested in research related to information communication technology (ICT) especially in green energy, networking, online system, programming, and security. I've grown interested in networking since 2012 where on that period and onward I was given a chance to directly manage networking devices such as switches, routers, and servers whether they are Allied Telesis, Cisco, Mikrotik, or other devices. At the same time I was looking for an operating system (OS) suited for networking, most people here said Linux had an upper edge. I started with Ubuntu to get familiar then a senior also a friend of mine introduced me to Backtrack 5, now I'm using its latest Kali Linux. There I also learned the word pentest which is an abbreviation to penetration testing and learn of so called open source software. Around the end of my undergraduate studies I was found that I was using Linux, and thankfully given a chance to work on a research of Linux embbeded system on wireless sensor network (WSN). There I went deep into the Linux itself and C programming which I must write a code to transmit images between Imote2 Linux WSN and apply image compression for efficiency.

I made that research as my bachelor thesis and graduated and now I would like to continue my study to master degree around the related field. I would like to apply to Graduate School ... on the program ... which I aim to further researching. I would like to continue studying related to ICT. I wanted know the latest online system, for example where we can follow a distant course through e-learning, not to exclude the large scale network involved. Other than that I would like to enhance my knowledge in hacking which both network security and web security are fundamental. Also I would like to learn of free opensource software in which I believe will be leading and auxilary in the future since for everyone is free to use and develop.

A slight improvement adding my experiences and more details about my abilities which is one of the information that we must show when applying for a job. However again, there was no proposal here of what I could contribute to and just showing what I could do. Then, I got rejected by Australian Awards and did not pass the interview for Fullbright. My time was running out and my surroundings are impatiend of my unemployed status, thus I was forced take a job no matter what it is.

My First Stressing Employment

johnny automatic assembling the engine

Why do I dare to write "stressing" in the heading? Because the higher ups said so that stress and overtime is the norm there and employees running away breaching the contract are many and if I want to escape as well go ahead. They pride themselves in a metaphore of school that if we last until the end of the contract, we will be proud graduates no matter how bad we performed. After that, employees move on or rare cases of continue working there.

This period was the first time in my life where I hated Sunday night very much and liked Friday noon very much. Why? because the haunting that Sunday night will last and have to wake up at 5 tomorrow to prepare going to work and the best days of back then was Friday night where I kept myself sane with movie cinema entertainment plus tasty foods and tasty drinks where usually day and night I eat at the cafeteria and the thought that I can sleep as much as I want and no need to worry about tomorrow Saturday where I do not have to worry about work. While it is true that I did not like Mondays and liked Saturdays in my primary and high school times but not as far as hating them like in these working days.

Wearing uniforms and working days from 08:00 - 20:30 is still something bearable as I was used to work hard volunteerily. However, those things became a great nightmare when my job is something not only I had zero experienced in but also zero knowledge in. In the interview, I explained clearly that I was a computer and network engineer but do you know what they put me into? Manufacture Engineer. It had been since high school that I was humiliated as someone stupid. It never happened in my college life because I pride myself as a strategist, planner, and often daydreamed of grand schemes so I am good a calculating my abilities. I was great, not because I was really great but I only took jobs that could do and I could even forsee how long I would take. When someone asked me fpr a complicated job for example, I would say that I needed 2 to 3 weeks for example, and if they do not want take the risk, I even dared to say that it is better to ask someone else. In this employment case was because I forced to since I was doubting the future result of my scholarship applications and was unclear with my plans. Thus, pushed me to this employment in an unfamiliar area where it should not even be like this that my original intention was only an intership where I would even pay so they would have understand my intention was only to study and gain experience and not have a high expectation. However, why an intership, just get employed with contract directly they said. They do not understand that an employment meant that I have to do well in the job and contribute much to the company where in my case would potentially lead to a disappointment. Wait, couldn't I just explained my background whenever I cannot do something? Would you care if you see a stupid employee? I may care but most people would not care and just scorn that employee for being stupid. Even if I initiatively explained my background, people probably are too lazy to listen. The reply most of the time, "if you know that, why did you even accept this job?". That's right, why did even accept that job? Because I was wavering, full of doubts, and unclear about my plans where that employment was my escape from the humiliation of unemployment. Ironically, it was an escape from one prison to another prison.

Despite my complains from the public perspective, I was blessed. Other than the rich knowledge and experience, I was given high salary compared to other fresh graduates, group housing provided with all the bills paid, transportation to my work place, free lunch, and free dinner if I stayed over time. Plus, my salary can be doubled if I worked overtime everyday where overtime was the norm so my salary was doubled in default. The everyday scolding and yelling are for the lazy and the fearful. Hard work are appreciated. Employees called it a hell hole because they fear their bosses. I don't, I have no hesitation when facing them, I tell whatever the situation truthfully, and if they don't like it, I don't care, and if they push the button, I'm not afraid to bite back, but what can I do in a work I have no knowledge in except for just listening to their anger? On the other hand if you are competent or good at what you do, you will dominate and lead instead. I saw the bosses relying on peers who have background, who were very good at manufacture engineering, and had passion in them. Me? I was an easy target for the first three months, and after that I knew at least the basic stuffs which is enough to not let them push me around as I covered my lack of brilliance with hard work. My seniors often afraid confronting my bosses, I did not understand the meaning of fear which is enough for to dominate after the 3 months.

Compared to my collegues on the same year as me, they are still under mentorship of their seniors while my mentor on taught me for about 2 weeks and released me to wild by myself since he was to busy to teach me. That suits me well, I went here and there, met people here and there, asked the appropriate people for the appropriate problems, and I volunteered to take the general manager's extra lessons and projects during every overtime after 17:00 - 20:30 if I did not have any main jobs at the time. Still, I did not want to stay there long as back then was not inline with my study which was computer network, server, and security at the time. In my workplace from 07:30 - 20:30 and 30 minutes each on the road, I only had 21:00 - 22:00 and Saturdays and Sundays for my own agenda. I was richer than most fresh graduates in my country, but what is the use of money if I do not spend them and there was no way I had time to start learning business and investing.

Light at The End of The Tunnel

railroad tunnel publicdomain

After three months I already accept my fate that I had to endure for 2 years, however a surprising news arrived at the fifth month. I read again and again, and read again and again that I could not believe I was accepted for MEXT scholarship in Japan! This was the month I worked the hardest because I was to happy that the light appeared at the end of the tunnel. Other than the previous cover letters, the followings are addition that added when I submitted to MEXT scholarship:

If I may propose a research I would like to propose about how much important security in e-learning system. I've learned of e-learning in my undergraduate studies, used it to follow some courses, and tried it myself in giving a course through e-learning. What I haven't heard about is its security, news if it had ever been hacked and how its impact to e-learning. So there's a question whether security is highly important to e-learning or not. I find this topic quite urgent since the development of opensource software, which unlike before there are lots of free pentest tools available. Since it's opensource the development is quite rapid because many people are involved, there's even OS specifically for pentest. Even if it's called pentest it's still a powerful hacking tools. More shocking fact is that these tools' simplicity are incredible, which means everyone can use with just a few studying.

I believe technology as one of the main aspect for a civilization to be advance, for a country to develop and that's why I pursue my career in technology. In the future I would like to be professional in technology, specialist in ICT. By continuing my study, I can contribute in the development of technology, and finally I want to participate in the world's summit.

Unlike before, I wrote what I planned to do and additionally I boasted big that I want to be on the world's summit one day. While I did wrote some sort of plan but the me now evaluated the writing was due to some sort of luck. The proposal lacks details like what kind of securities, why securities are important where I should have wrote a background story and if there was none, I should have wrote a future possibility or potential problem, and lastly the methods I are missing in my proposal. If not a method, at least an idea that can somewhat complete the story of my proposal. Maybe I am right that what I written above was not enough but there was an email interview and here is an important part that I wrote:

As of my career plans ofcourse I would like to be a professional in technology. If I could would like to continue for PhD/Dr degree which is still far since I'm still trying for Master degree.

What I wanted to do is to continuously participate in international events, specifically to contribute to the world in the development of technology, whether it be participating in international conference, collaborate research, or dive into society to help for the better.

In the future I would like to make one of my dreams come true, which is a unified world. Those are fantastic words but what I'm aiming for is to make each parts of the world seems closer where we could travel or adventure here and there, and easily get to know each part of the world. For example the distance between here Indonesia and Japan is 4,819 km physically far away, what I wanted is to make these two places seems likes it's just next door.

Physically transportation plays the most part, but what I could do is to make it seems close. With the existence of The Internet we can interact between countries as if we're neighbors. There's conventional email, today there are forums, social media, distant learning, even online games. I'll await in the future for virtual reality. So in my field of ICT I can make those physically far away seems close that could interact with each other as if face to face.

When I said even before I graduated I wanted to continue to graduated, I already wanted as far as to do PhD and I mentioned that in my written interview. While at that time it was just a mention and a desire, when I made to Japan, that mention was actually one of the determining factors as I reached the lab that I was already given more research to do because they knew that I wanted to continue to PhD they said while other Master's student are having it more leisure. I also mentioned that after I finish everything that I wanted to participate more in international events. I felt bad that my priorities changed today but it is still excuseable since we are still in COVID-19 Pandemic. At that time, I already gave up and leave everything to fate, so I might as well go with a bang in my final letter. I wrote in the future that I wanted to unify the world where we can go anywhere at anytime. The idea is actually a courtesy from a cinematic video game developed by Kojima Production Metal Gear Solid 4 Guns of The Patriot led by Hideo Kojima. The original story is that a man almost succesfully unified the world from the shadows where there are no longer any borders where we are just creatures walking on this world with no races and no nationality, we are a singularity but also a society as a whole. Now that I think about, maybe that statement was also a determining factor.

Anyway, as I was accepted, I worked the best that I could before I resigned. Though I hated the working system, I was grateful to the friends I made. Like in many places, they are pleasant people who helped me and took me out to have fun. I made to Japan and continue study in graduate school. I find it funny for some peers of mine are stressed from the study. For me, this is heaven compared to the 08:00 - 20:30 in uniforms and I forgot to mention that employees below managers are not allowed to bring their own computer devices and also not allowed to use the Internet. Even further, we cannot plugged our USB to transfer data, I even have to hack the Trend USB software. Well, I heard that some of my peers here are used to leisure work like playing games and watching Korean Drama movie many times because there are less work and most of them missed their family. While for me, I enjoyed the class, I enjoyed the research, I enjoyed the free electricity and very fast Internet connection, especially very thankful for the scholarship, and finally the first time in my life, I lived freely and independent. Aside from the classes and every monday to present my progress report, I was free to wake and sleep whenever I wanted, to go weherever I wanted, to eat whatever I wanted, and to meet whomever I wanted. Basically, I was free to make my own schedule where at the point when I did not have any classes anymore, I research and got indulged in entertainment depending on my mood until 5 in the morning, and then sleep until 2 in the afternoon and my schedule was constantly changing however I wanted and they did not complain because I deliver my progress report on time and frequently exceeded their expectation. Other than that, I have money to invest! Those were the start of my happiest time in my lifetime.

Mirror

Note

This is one of my Doctoral assignment from Advanced Computer Architecture II Course which has never been published anywhere and I, as the author and copyright holder, license this assignment customized CC-BY-SA where anyone can share, copy, republish, and sell on condition to state my name as the author and notify that the original and open version available here.

1. Introduction

Peripheral interface controller (PIC) is a family of microcontrollers made by Microchip Technology. A microcontroller is a one chip computer that include microprocessors, memories, and peripherals. PIC devices are popular with both industrial developers and hobbyists due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, serial programming, and re-programmable Flash-memory capability. They can be programmed to be timers, to control a production line, to control light and sound intensity by involving few sensors, and to perform other kind of tasks. The PIC microcontroller have five basic instruction cycle which are fetch, decode, execute, memory, and write (FDEMW) . [1]

2. Verilog HDL Design

This report’s design
Figure 1. This report’s design [2]

On the verilog hardware description language (HDL) design is based on Figure 1. This sections starts by constructing the arithmetic logic unit (ALU), bitmask, and W register. Then continue to design the program counter and return stack which its values to be sent to the instruction register where there is also decode and control behavior. Next is the design of special register, although the effective addressing is discussed in early part. After that the built module have to be connected to the firstly created ALU, bitmask, and W register. Lastly implement sleep and tristate buffer.

2.1 Arithmetic Logic Unit

ALU diagram
Figure 2. ALU diagram [2]

Code 1. Input and output of ALU

module alu ( CLK, CB, WE, B, FI, FO, CI, CO, DC, Z );
input CLK;// Clock
input [4:0] CB; // operation code
input WE; // Write enable for W register
input [2:0] B; // bit position
input [7:0] FI; // operand
input CI; // Carry in
output [7:0] FO; // dest bus
output CO; // Carry out
output DC; // Half carry
output Z; // Zero
reg HC; // half carry
reg [7:0] W;
reg [8:0] tmp;
reg [7:0] bit_mask;
wire sub;
assign sub = ( CB == `ISUB );

Code 2. Bitmask

always @( B )
case( B )
3'b000: bit_mask = 8'b0000_0001;
3'b001: bit_mask = 8'b0000_0010;
3'b010: bit_mask = 8'b0000_0100;
3'b011: bit_mask = 8'b0000_1000;
3'b100: bit_mask = 8'b0001_0000;
3'b101: bit_mask = 8'b0010_0000;
3'b110: bit_mask = 8'b0100_0000;
3'b111: bit_mask = 8'b1000_0000;
default: bit_mask = 8'bxxxx_xxxx; 
endcase
ALU add sub
Figure 3. ALU add sub [2]

Code 3. Up to add and sub

always @( CB or FI or W or HC or CI or bit_mask or sub )
begin
  HC = 1'b0;
  casex( CB ) `
    IPSW: tmp = { 1'b0, W }; // Pass W register value
    `ICLR: tmp = 9'b0_0000_0000; // Clear
    `IADD, `ISUB:
    begin { HC, tmp[3:0] }= {1'b0,FI[3:0]} + {1'b0, sub? ~W[3:0]:W[3:0]} + sub;
                 tmp[8:4] = {1'b0,FI[7:4]} + {1'b0, sub? ~W[7:4]:W[7:4]} + HC; 
	end

The verilog design of the ALU is based on the diagram on Figure 2. The input, output, and process looks clear which was implemented on Code 1, however the detail operation within the bitmask, ALU, and w register should be examined on Code 2, Code 3, and Code 4. The ALU operates between the value on the W register and the current input FI. For addition and subtraction, Code 3 should follow the diagram on Figure 3, while for other operations are not as complicated which is on Code 4. After that, the output can be written on Code 5. The operation definitions are available on Code 6 which the bit opcode from 2nd to 6th from left to right is used.

Code 4. Other Operations

`IDEC1, `IDEC2: tmp = { 1'b0, FI } - 1 ; // Decrement, Decrement and skip if 0
`IOR : tmp = { 1'b0, FI } | { 1'b0, W } ; // Logical OR
`IAND: tmp = { 1'b0, FI } & { 1'b0, W } ; // Logical AND
`IXOR: tmp = { 1'b0, FI } ^ { 1'b0, W } ; // Logical Exclusive OR
`IPSF: tmp = { 1'b0, FI } ; // Pass FI
`INTF: tmp = { 1'b0, ~FI } ; // Complement FI
`IINC1, `IINC2: tmp = { 1'b0, FI } + 1 ; // Increment, Increment and skip if 0
`IRRF: tmp = {FI[0], CI, FI[7:1]} ; // Rotate Right through Carry
`IRLF: tmp = {FI, CI} ; // Rotate Left through Carry
`ISWP: tmp = {1'b0, FI[3:0], FI[7:4]}; // nibble swap
`IBCF: tmp = {1'b0, FI} & {1'b0,~bit_mask} ; // bit clear
`IBSF: tmp = {1'b0, FI} | {1'b0, bit_mask} ; // bit set
`IBTF: tmp = {1'b0, FI} & {1'b0, bit_mask} ; // bit test
default: tmp = 9'bx_xxxx_xxxx;
end case
end

Code 5. Output, W Register, and Flags

// FO
assign FO = tmp[7:0] ;
// W Register
always @( posedge CLK )
if( WE ) W <= tmp[7:0] ; // Flag
assign CO = tmp[8] ; // Carry Borrow flag
assign DC = HC ; // Half carry flag
assign Z = (tmp[7:0] == 0) ; // Zero flag
endmodule

Code 6. ALU Operation Definition

`define IPSW 5'b00000 // Pass W
`define ICLR 5'b00001 // Clear
`define ISUB 5'b00010 // Sub
`define IDEC1 5'b00011 // Dec
`define IOR 5'b00100 // Or
`define IAND 5'b00101 // And
`define IXOR 5'b00110 // Xor
`define IADD 5'b00111 // Add
`define IPSF 5'b01000 // Pass F
`define INTF 5'b01001 // Not
`define IINC1 5'b01010 // Inc
`define IDEC2 5'b01011 // Dec
`define IRRF 5'b01100 // Rotate Right with carry
`define IRLF 5'b01101 // Rotate Left with carry
`define ISWP 5'b01110 // Nibble swap
`define IINC2 5'b01111 // Inc
`define IBCF 5'b100?? // Bit Clear F
`define IBSF 5'b101?? // Bit Set F
`define IBTF 5'b11??? // Bit Test F

2.2 Core Input, Output, and Register

Data Memory Map
Figure 4. Data Memory Map [2] [3]

Code 7. Input, Output, and Register for Core Module

// STATUS Register
`define STATUS { IRP, RP, nTO, nPD, Z, DC, C }
// IR
`define IRB IR[ 9:7]
`define IRK IR[ 7:0]
`define IRF IR[ 6:0]
`define IRA IR[10:0]
// Memory Address
`define A_INDF 7'b000_0000
`define A_PCL 7'b000_0010

module pic16core ( CLK, RST, RA, RB );
input CLK;
input RST;
inout [7:0] RA;
inout [7:0] RB;

parameter PROG = "program.mem";

// Special Register
reg IRP;
reg [1:0] RP;
reg nTO, nPD, Z, DC, C; // 03 83 // STATUS
reg [7:0] FSR; // 04 84
reg [7:0] PORTA, TRISA; // 05 85
reg [7:0] PORTB, TRISB; // 06 86
reg [4:0] PCLATH; // 0A 8A
reg [7:0] RAM[ 12 : 127 ]; // 0C-7F // DATA bus
reg [7:0] SDATA; // for special register
reg [7:0] RDATA; // for ALU operand
wire [7:0] WDATA; // for ALU result
wire [7:0] DDATA; // for Data RAM Read Data

// Flag data from ALU to Flag register
wire CO, DCO, ZO; // Control Signal
reg NOP_S; // Fetch cancel on CALL, GOTO
reg [4:0] ALU_CB; // ALU control
reg W_W; // Write enable for W register
reg C_W, DC_W, Z_W; // Write enable for Flag register (STATUS[2:0])
reg F_W; // Write enable for Data memory
reg WDT_C; // WDT clear
reg nTO_S, nTO_C; // nTO set and clear
reg nPD_S, nPD_C; // nPD set and clear
reg SLEEP; // Sleep mode
reg SLP_S; // Sleep mode set // Register
reg [12:0] PC; // Program Counter { PCH, PCL }
reg [13:0] IR; // Instruction Register

// Register
reg [12:0] PC; // Program Counter { PCH, PCL }
reg [13:0] IR; // Instruction Register

2.3 Effective Addressing

Direct and indirect addressing diagram
Figure 5. Direct and indirect addressing diagram [2] [3]

Based on Figure 5, Code 8 should write to RP if direct addressing, otherwise if indirect addressing IRP should be FSR.

Code 8. Affective addressing for core module

// Effective Address
wire [ 8 : 0 ] EA;
assign EA = ( `IRF == 0 ) ? { IRP , FSR [7:0] } : { RP , `IRF};

2.4 Program Counter and Return Stack

PC loading return stack
Figure 6. PC loading and return stack [2] [3]

For Code 9 about program counter and return stack, the value of PC is based the left diagram of Figure 6. When operation call, then the stack is pushed, and when operation return, then the stack is popped. The value of STKP should be based on the right diagram of Figure 6.

Code 9. Program counter and return stack

// Program Counter & Return Stack
reg [ 12:8 ] STK[0:7]; // Return Stack depth 8
reg [ 2:0] STKP; // Return stack pointer 4 bit
reg STK_PU; // Stack Push enable
reg STK_PO; // Stack Pop enable
reg PC_W; // Write enable for CALL, GOTO

// Program Counter
always @( posedge CLK )
if( RST ) PC <= 0; else // RESET
if( PC_W ) PC <= {PCLATH[4:3],IR[10:0] }; else // CALL, GOTO
if( F_W && EA [6:0] == `A_PCL ) PC <= { PCLATH[4:3], WDATA[7:0] }; else // write PCL register if( STK_PO ) PC <= STK[ STKP-1 ]; else // RETURN, RETLW
if( SLEEP || SLP_S ) PC <= PC ; else // SLEEP mode
PC <= PC + 1;

// Return Stack
always @( posedge CLK )
begin
if( RST ) STKP<= 0 ; else // for Empty
if( STK_PU ) begin STK[ STKP ] <= PC ; STKP<= STKP+1; end else // for CALL
if( STK_PO ) STKP<= STKP-1; // for RETxx
end

2.5 Instruction Memory and Register

instruction register shared memory
Figure 7. instruction register and shared memory [2]

Code 10. Instruction memory and Register

// Instruction Memory (8k word)
reg [ 13 : 0 ] IMEM[ 0 : 8195 ];
initial
begin
$readmemh( PROG, IMEM );
end

// Instruction Register
always @( posedge CLK )
if( NOP_S || PC_W || STK_PO || RST )
IR <= 14'b00_0000_0000_0000 ; else // if CALL, RET, cond.SKIP
IR <= IMEM[PC] ; // Instruction fetch

2.6 Decode and Control

To write Code 11, the instruction table and instruction details on the datasheet [3] should be referred. Code 11 is written starting from first two bits of the instructions then the next 4 bits of the instructions. Refer again to the datasheet [3] of which status are affected. Unfortunately, sleep here is a repeat NOP.

Code 11. Decode and control

// Decode & Control
always @( IR or ZO )
  begin
    ALU_CB=IR[ 12 : 8 ];
    F_W=0; W_W=0; Z_W=0; DC_W=0; C_W=0; nTO_S=0; nTO_C=0; nPD_S=0; nPD_C=0; STK_PU=0;
    STK_PO=0; NOP_S=0; PC_W=0; WDT_C=0; SLP_S=0;
    case( IR[ 13 : 12] )
      2'b00 :
        begin
          W_W = ~IR[7] && IR[11:8] != 4'b0000 ;
          F_W = IR[7]; //same with W_W = IR[7] && |IR[11:8] meaning bit 8 is 1 and bit 9-12 isn`t 0
          case( IR[ 11 : 8 ] )
            4'b0000:
              case( IR[7] )
                1'b0: case( IR[ 6 : 0 ] )
                  7'b000_1000 : begin NOP_S=1 ; STK_PO=1 ; end // RETURN
               // 7'b000_1001: ; // RETFIE
                  7'b110_0011 : begin nTO_S=1; nPD_S=1; WDT_C=1; SLP_S=1 ; NOP_S=1 ; end // SLEEP
               // 7'b110_0100: ; // CLRWDT
                  default: ; // NOP
                  endcase
                1'b1: ; // MOVWF f
              endcase
            4'b0001: begin Z_W=1 ; end // CLRW, CLRF
            4'b0010: begin C_W=1 ; DC_W=1 ; Z_W=1 ; end // SUBWF
            4'b0011: begin Z_W=1 ; end // DECF
            4'b0100: begin Z_W=1 ; end // IORWF
            4'b0101: begin Z_W=1 ; end // ANDWF
            4'b0110: begin Z_W=1 ; end // XORWF
            4'b0111: begin C_W=1 ; DC_W=1 ; Z_W=1 ; end // ADDWF
            4'b1000: begin Z_W=1 ; end // MOVF
            4'b1001: begin Z_W=1 ; end // COMF
            4'b1010: begin Z_W=1 ; end // INCF
            4'b1011: begin NOP_S= (ZO==1) ? 1 : 0 ; end // DECFSZ
            4'b1100: begin C_W=1 ; end // RRF
            4'b1101: begin C_W=1 ; end // RLF
            4'b1110: ; // SWPF
            4'b1111: begin NOP_S=ZO ; end // INCFSZ
          endcase //IR
        end
        2'b01 :
        begin
          case( IR[ 11 : 10 ] )
            2'b00 : F_W = 1 ; // BCF f, b
            2'b01 : F_W = 1 ; // BSF f, b
            2'b10 : NOP_S=ZO ; // BTFSC f, b
            2'b11 : NOP_S=~ZO ; // BTFSS f, b
          endcase
        end
        2'b10 :
            begin
              PC_W = 1 ; NOP_S = 1 ;
                case( IR[ 11 ] )
                  1'b0 : STK_PU = 1 ; // CALL
                  1'b1 : ; // GOTO
                endcase
              end
              2'b11 :
              begin
                W_W= 1 ;
                casex( IR[ 11 : 8 ] )
                  4'b00xx : begin ALU_CB=`IPSF ; end // MOVLW k //--> pass in ALU to W //
                  4'b01xx : begin ALU_CB=`IPSF ; STK_PO = 1 ; NOP_S = 1; end // RETLW k
                  4'b1000 : begin ALU_CB=`IOR ; Z_W = 1 ; end // IORLW k
                  4'b1001 : begin ALU_CB=`IAND ; Z_W = 1 ; end // ANDLW k
                  4'b1010 : begin ALU_CB=`IXOR ; Z_W = 1 ; end // XORLW k
                  4'b110x : begin ALU_CB=`ISUB ; C_W=1 ; DC_W=1 ; Z_W = 1 ; end // SUBLW k
                  4'b111x : begin ALU_CB=`IADD ; C_W=1 ; DC_W=1 ; Z_W = 1 ; end // ADDLW k
                endcase
              end
            endcase
          end // always @ ( IR or ZO )

2.7 Special Register

specialregister
Figure 8. Special register [3]

Code 12 about special register is based on Figure 3 memory map for the written bits and Figure 8 about special register itself for its values.

Code 12. Special register

// Special Register
// Write
always @( posedge CLK or posedge RST )
  begin
    if( RST )
      begin
        C = 0 ;
        DC = 0 ;
        Z = 0 ;
        IRP = 0 ;
        RP = 2'b00 ;
        nTO = 1 ; // nTO=1 on Power-on
        nPD = 1 ; // nPD=1 on Power-on
        FSR = 0 ; PCLATH = 5'b00000 ;
        PORTA = 8'b0000_0000 ;
        TRISA = 8'b1111_1111 ; // All ports for input
        PORTB = 8'b0000_0000 ;
        TRISB = 8'b1111_1111 ; // Table page 18-20
      // All ports for input
         end
       else
         begin
           // STATUS
           if( C_W ) C = CO ;
           if( DC_W ) DC = DCO ;
           if( Z_W ) Z = ZO ;
           if( nPD_S ) nPD = 1'b1;
           if( nPD_C ) nPD = 1'b0;
           if( nTO_S ) nTO = 1'b1;
           if( nTO_C ) nTO = 1'b0;
           // Register Write
           if( F_W ) //pic16_behaviour page 41
             casex( EA ) //effective address
           // 9'b?0_000_0001: TMR0 = WDATA; // 01 101 Described TMR0 part //find in address table
           // 9'b?1_000_0001:`OPTION = WDATA; // 81 181
           // 9'b??_000_0010: PCL = WDATA; // 02 82 102 182 Described PC part
              9'b??_000_0011:`STATUS = WDATA; // 03 83 103 183
              9'b??_000_0100: FSR = WDATA; // 04 84 104 184
              9'b00_000_0101: PORTA = WDATA; // 05
              9'b01_000_0101: TRISA = WDATA; // 85
              9'b?0_000_0110: PORTB = WDATA; // 06 106
              9'b?1_000_0110: TRISB = WDATA; // 86 186
              // 9'b??_000_0111: ; // 07
              // 9'b??_000_1000: ; // 08 EEDATA not implement
              // 9'b??_000_1001: ; // 09 EEADR not implement
              9'b??_000_1010: PCLATH = WDATA[4:0]; // 0A 8A 10A 18A
              // 9'b??_000_1011:`INTCON = WDATA; // 0B 8B 10B 18B
            endcase
          end
        end

Code 13. Data RAM

// Data RAM (Write)
always @( posedge CLK )
  begin
    if( F_W && ( EA[6:0] >= 7'b001_1000 ) ) RAM[ EA[6:0] ] <= WDATA ; //12-127 PIC16 behaviour p.46 //light behaviour p.41 //Effective Address only 7bit not 9bit start from 12 //store RAM to WDATA
  end
// Selecter for Special Register
always @( IR or PC or EA or IRP or RP or nTO or nPD or Z or DC or C // STATUS
                  or FSR or RA or TRISA or RB or TRISB or PCLATH )
  casex( EA )
    // 9'b?0_000_0001: SDATA = TMR0;
    // 9'b?1_000_0001: SDATA =`OPTION;
    9'b??_000_0010: SDATA = PC[7:0] ; // PCL
    9'b??_000_0011: SDATA =`STATUS ; // STATUS
    9'b??_000_0100: SDATA = FSR ; // FSR
    9'b00_000_0101: SDATA = PORTA ; // RA
    9'b01_000_0101: SDATA = TRISA ; // TRISA
    9'b?0_000_0110: SDATA = PORTB ; // RB
    9'b?1_000_0110: SDATA = TRISB ; // TRISB
    9'b??_000_1010: SDATA = {3'b000, PCLATH }; // PCLATH //because SDATA is 9 bit and PCLATH is only 6 bit, we need to add 3 bit before PCLATH // 9'b??_000_1011: SDATA =`INTCON;
    default: SDATA = 8'bxxxx_xxxx;
  endcase
// Data RAM Read
assign DDATA = RAM[EA[7:0]] ;

2.8 Data Path

Data path to ALU
Figure 9. Data path to ALU [2]

Code 14. Data selector for ALU

// Data selector for ALU operand
always @( IR or EA or DDATA or SDATA )
  begin RDATA <= 8'bxxxx_xxxx ;
  if( &IR[13:12] ) RDATA <= `IRK ; else //
    casex( EA )
      9'b??_000_0010: RDATA <= SDATA ; // PCL
      9'b??_000_0011: RDATA <= SDATA ; // STATUS
      9'b??_000_0100: RDATA <= SDATA ; // FSR
      9'b0?_000_0101: RDATA <= SDATA ; // PORTA, TRISA
      9'b0?_000_0110: RDATA <= SDATA ; // PORTB, TRISB
      9'b??_000_1010: RDATA <= SDATA ; // PCLATH
      default: RDATA <= RAM[EA[7:0]] ; // Shared memory
    endcase
  end

2.9 ALU Initiate

ALU initiate diagram
Figure 10. ALU initiate diagram [2]

Code 15. ALU initiate code

// Execute
   alu i_alu ( .CLK(CLK), .CB(ALU_CB), .WE(W_W), .B(`IRB),
	       .FI(RDATA),
	       .FO(WDATA),
	       .CI(C), .CO(CO), .DC(DCO), .Z(ZO) );

2.10 Sleep

Back on Code 11, sleep is a repeat NOP. Here on Figure 9, waking up from sleep is not implemented, sleep forever but can be reset.

Sleep diagram
Figure 11. Sleep diagram [2]

Code 16. Sleep implementation

// Sleep mode
always @( posedge CLK or posedge RST )
begin
  if(RST) SLEEP <= 0; else //0 mean run
  if(SLP_S) SLEEP <= 1; //1 mean execute the sleep mode
end

2.11 Tristate Buffer

Tristate buffer diagram
Figure 12. Tristate buffer diagram [2]

Code 17. Tristate buffer implementation

// Tristate buffer for GPIO
assign RA[0] = ( TRISA[0] ) ? 1'bZ : PORTA[0];
assign RA[1] = ( TRISA[1] ) ? 1'bZ : PORTA[1];
assign RA[2] = ( TRISA[2] ) ? 1'bZ : PORTA[2];
assign RA[3] = ( TRISA[3] ) ? 1'bZ : PORTA[3];
assign RA[4] = ( TRISA[4] ) ? 1'bZ : PORTA[4];
assign RA[5] = ( TRISA[5] ) ? 1'bZ : PORTA[5];
assign RA[6] = ( TRISA[6] ) ? 1'bZ : PORTA[6];
assign RA[7] = ( TRISA[7] ) ? 1'bZ : PORTA[7];
assign RB[0] = ( TRISB[0] ) ? 1'bZ : PORTB[0];
assign RB[1] = ( TRISB[1] ) ? 1'bZ : PORTB[1];
assign RB[2] = ( TRISB[2] ) ? 1'bZ : PORTB[2];
assign RB[3] = ( TRISB[3] ) ? 1'bZ : PORTB[3];
assign RB[4] = ( TRISB[4] ) ? 1'bZ : PORTB[4];
assign RB[5] = ( TRISB[5] ) ? 1'bZ : PORTB[5];
assign RB[6] = ( TRISB[6] ) ? 1'bZ : PORTB[6];
assign RB[7] = ( TRISB[7] ) ? 1'bZ : PORTB[7];
endmodule

3. Simulation

Test simulation of the ALU code
Figure 13. Test simulation of the ALU code [2]
Waveform in simvision for ALU
Figure 14. Waveform in simvision for ALU [2]

All the codes to conduct the simulation are available online [4]. For solely testing the ALU, follow Figure 13 which are about generating the clock, and testing operations starting from PASSF, subtraction, until bit test. Figure 13 compiles the test sequence from text format into verilog HDL format using make_vector.pl binary. Then these files including Code 1-6 is compiled using verilog binary. The waves can be examined using simvision which can be shown on Figure 14. All the wave values are shown in hexadecimals. CB shows the executed operation. It is seen the W register becomes 1 when performed an increment operation, and reduced to 0 when subtract operation was performed, note that HC and CO has started to become affected. After that is logical operation where the result can be seen on FO as well. In the ends of this simulation is where the bit manipulation operations are performed where the B and bitmask variables are affected.

Waveform in simvision for ALU
Figure 15. Test simulation of PIC core [2]
Waveform in simvision for PIC core
Figure 16. Waveform in simvision for PIC core [2]

Figure 15 shows the diagram of testing the PIC16 core. The program.asm shows that only 10 operations are tested [4]. Next it have to be converted into an assembly file using gpasm which then the format have to be converted. After that the PIC16 core whole files [4] can be compiled using verilog and the waves can be seen using simvision on Figure 16. The first part of the test should bitset the RP, clear W, set TRISB to 00h, bitclear RP. The next operations are to do ten times addition of ten. DData, RData, and WData should look consistent. First the value should be 0A which is hexadecimal of 10, then it should increase to 1B and everytime added by 10. Note that the decrements are also shown from 0A until 01. In the end the result is 37 and will be transferred to PORTB. The last operation is sleep. Note that the design on this report does not implement everything from the original as shown on Table 1.

Table 1. Original PIC16 versus this report’s design

PIC16Original ThisReport’s Design
Pipeline 4 cycles /1 stage 1 cycle / 1stage
Clock Selectable Externalonly
Sleep mode Low powermode Repeat NOP
Watch DogTimer Available None
Timer Available None
Prescaler Available None
Interrupt Available None
Flashmemory Available None

4. Implementation

The verilog HDL codes can be implemented in FPGA. On this report Nexys4 DDR board is used on Figure 17 and Vivado software is used to synthesize the code. The LED should show 110111(2) which is 37 that is the result of the addition.

Nexys4 DDR board
Figure 17. Nexys4 DDR board

5. Reference

  1. https://en.wikipedia.org/wiki/PIC_microcontroller
  2. M. Kuga, “PIC_behavior20180124”, Supplied Course Material, 24-01-2018.
  3. Microchip, “16F84A-35007b”, PIC16F84A Data Sheet , 2001.
  4. https://github.com/0fajarpurnama0/Programming-Practice/tree/master/verilog/PIC16

Mirrors

Graphene Art

This is one of my Doctoral assignment from Current Science and Technology in Japan Course which has never been published anywhere and I, as the author and copyright holder, license this assignment customized CC-BY-SA where anyone can share, copy, republish, and sell on condition to state my name as the author and notify that the original and open version available here.

Graphene is a single layer of carbon atoms arranged in interconnected hexagonal lattice. It attracts the attention of lots of researchers, some calls it a wonder material, a miracle substance, or a substance that made people confused that it is substance that is only found in a comic book, all due to its amazing properties. It is one atom thick, conducts electricity better than silver, it conducts heat better than diamond, it is stronger than steel, it is lighter than feather, it is transparent, and it is bendable. Examples application possibilities are can replace a silicon transistors to graphene transistors in computers which can raise the frequency ten times from 100 to 1000 gigahertz, it can be used to make an unbreakable device screen, and as a better material for water disalination. Graphene was founded in 2004 by Andre Geim and Konstantin Novoselov from University of Manchester. They used a simple method using scotch tape to peel off graphite (the lead of a pencil) or stacks of graphene sheets into a single graphene sheet. Although graphene have huge amazing properties, it is still a future material because it is very difficult to produce and very expensive for mass production. [1] [2] [3]

Since graphene is very difficult and expensive to produce, researchers divides their attention to the graphene’s derivatives. Though its derivatives have less amazing properties, the properties can be tuned by going through certain processes. One of its derivatives is graphene oxide is a single-atomic layered material, made by the powerful oxidation of graphite. It can be said as an oxidized form of graphene laced with oxigen containing groups. It is considered easy to process since it is dispersible in water (and other solvents), and it can even be used to make graphene. It is commonly sold in powder form, dispersed, or as a coating on substrates. There are four basic methods of synthesizing graphene oxide which are Staudenmaier, Hofmann, Brodie and Hummers. [4]

Reference

  1. Graphene: The Next Big (But Thin) Thing, https://www.youtube.com/watch?v=Mcg9_ML2mXY [online]
  2. What Is Graphene - A Simplified Introduction, https://www.youtube.com/watch?v=WEnO6AJeP7k [online]
  3. New Discovery Could Unlock Graphene's Full Potential, https://www.youtube.com/watch?v=J0ZMi83oUjk [online]
  4. Graphene Oxide: Introduction and Market News, https://www.graphene-info.com/graphene-oxide [online]
  5. Featured Image: https://live.staticflickr.com/7250/14006201292_720f38b57c_b.jpg

Mirrors

Note

This is one of my Doctoral assignment from Current Science and Technology in Japan Course which has never been published anywhere and I, as the author and copyright holder, license this assignment customized CC-BY-SA where anyone can share, copy, republish, and sell on condition to state my name as the author and notify that the original and open version available here.

Pipelining for microprocessor

A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit (CPU) on a single integrated circuit (IC) chip containing millions of very small components including transistors, resistors, and diodes that work together [1]. The traditional microprocessor is too simple, but it is good to be explained in the class. The traditional one have five instructions which in order are fetch, decode, execute, memory, and write. In Figure 1 is seen that the program counter accesses the instruction memory, then the register fetch the instruction, next the instruction is decoded by the decoder, later it is sent to the arithmetic logic unit (ALU) and execute the instruction, finally the result is stored in the data memory and written into the register [2].

Simple Microprocessor Diagram
Figure 1. Simple Microprocessor Diagram

Pipelining is a technique to speed up the processing. Without pipelining the processor will have to wait until the whole 5 steps finishes before it can execute a new one, in other words serial processing. However pipelining allows the processor to start processing the next instruction without waiting until the previous instruction processing is finished, in other words parallel processing. Figure 2 showed the simplest illustration, but the technique have grown vast, for examples there are parallel operation, superscalar, super pipelining, and very long instruction word (VLIW). There are also data dependency problems such as flow, control, anti, intput, and output that prevents performance improvement. There are some techniques such as data forwarding, and dynamic code scheduling. [3]

Simple Pipelining Illustration
Figure 2. Simple Pipelining Illustration

GPGPU and CUDA

GPGPU was originally graphic processing unit (GPU) which is to process graphics, whether they are 2D (dimension) or 3D, still picture or moving picture (movie), and there are also animations and games, not to forget that the monitor is refreshing around sixty times a second. Just to process a single graphic took a lot of math or algorithms which is very heavy for the CPU which is why back then engineers created GPU solely to handle graphics. Today an innovation was made that GPU can be used for general purpose, and now comes the term general purpose graphic processing unit (GPGPU). [4]

Respectively the current intel i7 processor have 4 processing units (cores) while a GPGPU can have hundreds of cores, the current Geforce GTX 1080 Ti have 3584 cores. Figure 3 showed an illustration of CPU versus GPU. The essence of GPGPU is parallel processing (most people agree back when it was a GPU, it was used to parallel process the pixels in graphics). Nvidia created CUDA which is a parallel computing platform and programming model that allows to utilize their GPUs into GPGPUs. The simplest example is performing a loop program for example a hundred loops. In a CPU the loops is processed in serial order from one to a hundred, while in GPGPU the hundred loops are processed in an instant (depending on the number of cores). The processing speed greatly increases, I have example codes in C, C++, python, octave, and R which compares running in CPU and GPGPU using CUDA and OpenACC [5]. However GPGPU can only run non-specialized processes, which why CPU is still needed. The theory is long, but simply the process is first defined in the CPU, then the CPU divides the process to the cores in GPGPU, lastly the GPGPU returns the result to the CPU.

Illustration of CPU vs GPU
Figure 3. Illustration of CPU vs GPU (courtesy of http://www.hpc.co.jp/gpu_solution.html)

Open MP

Shared memory
Figure 4. Shared memory [6]

Openmp stands for open multiple-processing, it is an application program interface (API) that provided parallelism in shared memory through the implementation of multi-threading. Since it is in shared memory, openmp is only utilizable on multi-core CPUs, where shared memory is a certain space on the memory to be shared by other cores on the CPU. The other keyword is thread, where it is the smallest unit of a process which can be scheduled. A process can be single thread or multi-thread. Openmp allows the threads to run in parallel speeding the process and optimizing the use of resources. The core elements of OpenMP are the constructs for thread creation, workload distribution (work sharing), data-environment management, thread synchronization, user-level runtime routines and environment variables. Openmp supports C, C++, and fortran. Back on my coding in openacc [5], the pragma directive “acc” can be changed to “omp” to use openmp in the code. [6]

Parallel thread illustration
Figure 5. Parallel thread illustration [6]

Open CL

Opencl stands for open computing language. Although mostly today people elevate it for its parallelism, opencl is not just parallelism but an open standard computing language which supports heterogeneous or many kinds of systems such as CPUs, GPUs, digital signal processors (DSPs), mobiles, and even FPGAs. There are many more devices that it supports, unlike CUDA which only supports Nvidia devices. Although CUDA is great for personal projects because it has more libraries and better programming interface, but if the product is to be commercialized, then opencl is preferable because it supports many devices. Also if purely want to make the code as open as possible, opencl is best because of its compatibility. The code that was made can be portable to all sort of devices. The coding of opencl is based on C99, but today it also supports C++11. The concept parallelism is almost the same as CUDA, openmp, and openacc. [7]

Reference

  1. https://simple.wikipedia.org/wiki/Microprocessor
  2. Pipelining in a Processor - Georgia Tech - HPCA: Part 1, https://www.youtube.com/watch?v=eVRdfl4zxfI
  3. K. Morihiro, “Recent Computer System Technology”, Presentation Slide for Current Science and Technology in Japan Course.
  4. Introduction to GPGPU - General Purpose Computing on GPUs, https://www.youtube.com/watch?v=xKxG0fSymKc
  5. https://github.com/0fajarpurnama0/Programming-Practice/tree/master/cuda
  6. https://computing.llnl.gov/tutorials/openMP/
  7. Introduction to OpenCL, https://www.youtube.com/playlist?list=PLiwt1iVUib9s6vyEqdpcgAq7NBRlp9mAY

Mirrors

material exploration discovery design

Note

This is one of my Doctoral assignment from Current Science and Technology in Japan Course which has never been published anywhere and I, as the author and copyright holder, license this assignment customized CC-BY-SA where anyone can share, copy, republish, and sell on condition to state my name as the author and notify that the original and open version available here.

Material Exploration and Discovery

Materials have been one of the based of technologies for millennia. Airplanes, accessories, apparels, buildings, cars, computers, televisions, weapons, almost every object we know is made up of materials. The field of material engineering, science, and those related became very famous and important to advance technology.

Before the 17th century is an age of exploration. There were many adventures/explorers back then who traveled the lands, and sailed the seas, finding new territories. They discovered stones, irons, bronzes, silvers, golds, diamonds, aluminiums, minerals, and many other resources to be used in people’s live. Starting on the 17th century is an age of discovery where many alchemist, philosophers, and scientist research and perform experiments which birth for examples the theory of atoms by John Dalton, polymers and molecules by Hermann Staudinger, electricity by Thomas Edison, engine by Edward Butler, and more material properties and process were found on this age. It is mostly due to the advance in engineering and other related disciplines that invented tools such as microscope, pyrometer, and x-ray. These led to many inventions such as electronic devices, vehicles and many other tools and machines that shaped this modern era. Today a new age is approaching. The field of materials science and engineering is shifting into a more systems based approach to materials innovation and toward materials design in which researchers can predict new materials they would like to have rather than having to discover them. [1]

Material Design

The coming age is the age of design. With the discovery of many raw materials, processes, and theories, researcher may now utilize these accumulated data to design new materials, depending on the demands such as conductivity, strength, elasticity, resistance, texture, and many other features. Some examples of new materials today are cheap carbon fibers, nano crystals for solar harvesting and quantum computing, semi conductor materials, and our own kumadai magnesium alloy. Designing can be through calculations, computations, and simulations, which can greatly reduce the cost since there is less need for experiments and trials, in other words less wasting raw materials and reducing the risks of fail experiments which is uncertain of how much can be loss. However with the vast amount of data there is a limit to how fast a human can perform. Therefore researchers turn to computers that can perform millions of instructions per seconds, in other words by utilizing computers researchers can obtain much faster results which saves time. [2]

My Suggestion from Computer Science

My role in the field of computer science and electrical engineering is to develop applications and computer devices to assist researchers in material science and engineering. The very basic that can be done is to increase the computer’s hardware performance where the basic units are computer processing unit (CPU), random access memory (RAM), hard drive (HD) or disk storage, and graphic processing unit. Hardware is already the major attention of many big companies. For hardware also there are many collaboration from many disciplines including material science and engineering. For example the CPU’s transistors are made of silicons, imagine if graphene is made available to be implemented in the transistors, it can make computer 10x faster. Another example is the heat sink which looks simple but vital, without the help of material experts, computers will be facing overheat problems by now.

Other than basic hardware, there are accelerators such as general purpose graphic processing unit (GPGPU) and field programmable array (FPGA). These two supports parallel processing, and was tested to able to speed up a program up to 100x. Recently, material computations not only uses regression analysis alike, but also uses machine learning such as neural network. Although I’m not sure in the field of material science and engineering itself, but in computer science we are used to train big data where on a regular computer may usually take days, which is why we incorporate accelerators such as these (GGPU and FPGA). If it is similar in material computations, then accelerators can be utilized. Although utilizing accelerators requires to reconfigure the material computation program or simulator, sometimes reprogramming is required, these can be done by a programmer, Nvidia provides cuda libraries [3]. Aside from accelerators, today portable computer devices are trending such as micro-controller Arduino, single board computers such as Raspberry Pi [4], and some sensor boards. They be used on the field like in caves, forest, and mines for example because they are hand carry device, very small (the size of a hand), and low energy consumption. While usually is not a good idea to carry computers to the field, it is no problem in carry these devices and they can perform almost as good as a computer.

Lastly other than hardware are software and network. There many software available to perform analysis, even there are specific simulators for material experts. However most of the software known and used today are for personal use, while today the work environment in computers are slowly integrating to the cloud, another way of saying is that work environment is no longer personal but connected, collaborated with other users on the computer network. The integrated computational materials engineering (ICME) system which have a web interface and database is quite close with the cloud environment [2]. There has not exist an online material simulator, but it is possible make. On a certain a website in cavasmol there are people who had created some sort of web molecule simulator [5]. Although basic communications can be achieved through emails, messengers, and social networking services (SNSs), a collaboration is yet to be available for online collaborations of material computation For example in my field of computer science there is a platform called github to collaborate on codings [6]. This is something we can assist and collaborate in the future.

Reference

  1. G. B. Olson, Pathways of Discovery Designing a New Material World, Science Magazine, pp. 993-998, vol 288, 12 May 2000. [online] www.sciencemag.org.
  2. D. S. SHIH, Materials Science & Engineering for Aerospace Slide, Current Science and Technology in Japan Class, Kumamoto University, 31 October 2017.
  3. Nvidia Corporation, CUDA Zone. [online] access: 12 November 2017, https://developer.nvidia.com/cuda-zone
  4. Single Board Computer. [online] access: 12 November 2017, https://en.wikipedia.org/wiki/Single-board_computer
  5. CanvasMol. [online] access: 12 November 2017, http://alteredqualia.com/canvasmol/
  6. Built for Developers. [online] access: 12 November 2017, https://github.com/

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